Application of a Meta-Viterbi algorithm for communication systems without intersymbol interference

ABSTRACT

Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2 t  states. In a representative embodiment, the Non-ISI Meta-Viterbi detector performs χ+2 t 2 t  add, compare, and select operations.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application makes reference to:

U.S. application Ser. No. ______, (Attorney Docket No. 16001US01)entitled “META-VITERBI ALGORITHM FOR USE IN COMMUNICATION SYSTEMS”,filed Feb. 3, 2005.

The above stated application is hereby incorporated herein by referencein its entirety.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not Applicable

MICROFICHE/COPYRIGHT REFERENCE

Not Applicable

BACKGROUND OF THE INVENTION

It is well known that the Viterbi algorithm may be used for the maximumlikelihood detection of data. In the absence of intersymbol interferenceand when using the linear block coding rate (χ−t)/χ, the detection ofdata may be accomplished by using a Viterbi detector with 2^(t) states.However, when using linear block coding of rate (χ−t)/χ, in which t bitsof parity are encoded in a codeword of length χ, the Viterbi algorithmrequires performing χ2^(t) (χ times 2^(t)) add, compare, select (ACS)operations. Unfortunately, performing a large number of ACS operationsis sub-optimal since the implementation complexity also increases.

The limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of skill in the art, throughcomparison of such systems with some aspects of the present invention asset forth in the remainder of the present application with reference tothe drawings.

BRIEF SUMMARY OF THE INVENTION

Various aspects of the invention provide a system and/or method fordetecting and correcting one or more data bit errors transmitted througha communication channel, wherein the communication channel does notexhibit any intersymbol interference, substantially as shown in and/ordescribed in connection with at least one of the following figures, asset forth more completely in the claims.

These and other advantages, aspects, and novel features of the presentinvention, as well as details of illustrated embodiments, thereof, willbe more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a functional block diagram of an error detection andcorrection system that utilizes a conventional Viterbi Algorithm todecode a linear block code transmitted through a communication channel,in the absence of intersymbol interference (ISI).

FIG. 1B is a functional block diagram of a system that utilizes theMeta-Viterbi Algorithm in accordance with an embodiment of theinvention.

FIG. 2 is a functional block diagram describing a computationalcircuitry of a Non-ISI Meta-Viterbi detector that is used in determininga preferred set of error events, in accordance with an embodiment of theinvention.

FIG. 3A is a table illustrating the computation of cumulative parity andcumulative weight of a subset of error events (subset of H={e₁,e₂, . . .,e₁₅}) associated with a four-bit parity codeword, in accordance with anembodiment of the invention.

FIG. 3B is a diagram illustrating the 16 state Meta-Viterbi trellis pathtaken when the error events chosen correspond to {e₃, e₇, e₁₀, e₁₅}, asdescribed in relation to FIG. 3A, in accordance with an embodiment ofthe invention.

FIG. 4 illustrates a portion of a Meta-Viterbi trellis diagram inaccordance with an embodiment of the invention.

FIG. 5 is a diagram illustrating the selection of a path having lowestcumulative event weight, when two paths merge in a Meta-Viterbi trellis,in accordance with an embodiment of the invention.

FIG. 6 is a functional block diagram of a Non-ISI Meta-Viterbi detectorin accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Various aspects of the invention provide a system and method ofdetecting and correcting data bit errors that occur when a data streamis transmitted through a communication channel. The data bit errors maybe detected and corrected by way of transmitting a sequence ofcodewords. The codewords may incorporate or encode one or more paritybits into the transmitted data. The codewords are used in the detectionand correction process to recover the data transmitted. The method asdescribed herein utilizes what is referred to as a Meta-ViterbiAlgorithm for use in communication channels that do not exhibitintersymbol interference (ISI). Hereinafter, this method may be termedor referred to as a Meta-Viterbi Algorithm. The system that performs thedetection and correction as described herein may be termed a symboldetector and Non-ISI Meta-Viterbi detector.

In a representative embodiment, the channel may comprise a wirelinecommunications channel. In another representative embodiment, thechannel may comprise any communications transmission channel in whichISI is absent. Aspects of the invention provide performance that isequivalent to that provided by using the Viterbi Algorithm with 2^(t)states. However, various aspects of the invention provide a significantreduction in implementation complexity compared with that provided byusing the Viterbi Algorithm to detect codewords. When using the ViterbiAlgorithm having codeword length χ and t parity bits that results in alinear block coding of rate (χ−t)/χ, maximum likelihood detectionrequires the use of 2^(t) states run over χ steps. In terms ofimplementation complexity, the Viterbi algorithm requires performing atotal of χ2^(t) (χ multiplied by 2^(t)) add, compare, select (ACS)operations. In contrast, the Meta-Viterbi Algorithm may be performedusing only a total of χ+2^(t)2^(t) or χ+2^(2t) operations.

Various aspects of the invention implement at least a method and asystem of determining an optimum set of one or more error eventsassociated with a parity syndrome of a transmitted codeword. Eachtransmitted codeword is associated with an optimal set of one or moreerror events. The set of error events may be used to correct thecodeword by way of using its parity syndrome. The optimal set of one ormore error events is associated with a minimum cumulative event weightcomputed by a path formed from the decision branches of a trellisdiagram. The path traverses one or more steps corresponding to the errorevents associated with the codeword. The set or error events may bedetermined by using the parity syndrome and cumulative parity of thecodeword. A path or route is taken over a decision tree or trellisdiagram by way of one or more decision branches. The branch takencorresponds to whether a particular error event occurs in a codeword.Each of the one or more paths is associated with an event weight. Thecumulative weight may be found by summing the event weights of thebranches used to create the path of a codeword. The path with thesmallest cumulative weight is chosen as the optimal solution forcorrecting the codeword. Consequently, the set of error eventsassociated with this path is used to correct the received codeword. Thecumulative parity at the last step of the path may coincide with theparity syndrome of the received codeword.

FIG. 1A is a functional block diagram of an error detection andcorrection system that utilizes a conventional Viterbi Algorithm todecode a linear block code transmitted through a communication channel,in the absence of intersymbol interference (ISI). The system comprises alinear block encoder 104, a noise source 108, and a conventional Viterbidetector 112. As illustrated, a block of bits, ω=(ω₁, . . . ,ω_(χ−t)),comprising (χ−t) bits is input into a linear block encoder 104 prior totransmission through the communication channel. The linear block encoder104 outputs a codeword, ζ=(ζ₁, . . . , ζ_(χ)), that contains a total ofχ bits. One may denote a linear operator that generates a paritysyndrome for each codeword: Φ: {0,1}^(χ)→{0,1}^(t). Since the codewordis typically transmitted through a noisy communication channel, a noisesource 108 is applied to the communication channel. In a representativeembodiment, the noise source 108 may generate independent identicallydistributed noise into the communication channel. In yet anotherrepresentative embodiment that is not illustrated, data-dependent noisemay be added to the communication channel. In the embodiment illustratedin FIG. 1A, the noise output by the noise source 108 is added to thecodeword, ζ, such that a codeword, ξ, is input into a conventionalViterbi detector 112. The sequence of codewords received by the Viterbidetector 112 is represented by the variable ξεR^(χ). The Viterbidetector 112 utilizes 2^(t) states over χ steps in the detection andcorrection process. The Viterbi detector 112 determines a correctedcodeword ν⁽⁰⁾, given by the equation:${v^{(0)} = {\underset{x \in \Xi}{\arg\quad\max}{P( {\xi\text{❘}x} )}}},{{{where}\quad\Xi} = {\{ {{x \in {\{ {0,1} \}^{\chi}\text{❘}{\Phi(x)}}} = 0} \}.}}$In the absence of ISI in the communication channel and with noise thatis independent and identically distributed,${\log\quad{P( {\xi\text{❘}x} )}} = {\sum\limits_{i = 1}^{i = \chi}{\log\quad{{P( {\xi_{i}\text{❘}x_{i}} )}\quad.}}}$

FIG. 1B is a functional block diagram of a system that utilizes theMeta-Viterbi Algorithm in accordance with an embodiment of theinvention. In a representative embodiment, the system may comprise awireline data communications channel that corrects one or more data biterrors of one or more codewords by way of utilizing the Meta-ViterbiAlgorithm. Of course, the system may comprise any type of communicationchannel without intersymbol interference. As illustrated, the systemcomprises a linear block encoder 154, a noise source 158, a symboldetector 162, and a Non-ISI Meta-Viterbi detector 166. Aspects of theinvention provide that the system shown in FIG. 1B processes codewordsin a more efficient manner by way of adding t bits of redundancy to eachcodeword, and allowing the Non-ISI Meta-Viterbi detector 166 to processthe codewords using 2^(t) states. Linear block coding may be used at thetransmitter, for example, to generate codewords having t bits of parity.Compared to the system described in FIG. 1A, the system in FIG. 1Breplaces the Viterbi detector with the symbol detector 162 and theNon-ISI Meta-Viterbi detector 166. As illustrated, a block of bits,ω=(ω₁, . . . , ω_(χ−t)), containing (χ−t) bits is input into the linearblock encoder 154 prior to transmission through the communicationchannel. The linear block encoder 154 outputs a codeword, ζ=(ζ₁, . . . ,ζ_(χ)), contains a total of χ bits. One may denote a linear operatorthat generates a parity syndrome for each codeword: Φ:{0,1}^(χ)→{0,1}^(t). Since the codeword is typically transmitted througha noisy communication channel, a noise source 158 is applied to thecommunication channel. In a representative embodiment, the noise source158 may generate independent identically distributed noise into thecommunication channel. The noise output by the noise source 158 is addedto the codeword, ζ, such that a codeword, ξ, is input into the symboldetector 162. The symbol detector 162 provides an output, referred to asa hard decision output that is used by the Non-ISI Meta-Viterbi detector166, for example. In a representative embodiment, a slicer makes adecision by quantizing a received sample to a particular value. Thevalue provides an estimate of the actual transmitted sample. The harddecision output provided by the symbol detector 162, ν, may be definedby the following equation:$v = {{\underset{x \in {\{{0,1}\}}^{\chi}}{\arg\quad\max}\quad\log\quad{P( {\xi\text{❘}x} )}} = {\underset{x \in {\{{0,1}\}}^{\chi}}{\arg\quad\max}{\sum\limits_{i = 1}^{i = \chi}{\log\quad{{P( {\xi_{i}\text{❘}x_{i}} )}.}}}}}$The hard decision output is used by the Non-ISI Meta-Viterbi detector166 to generate a soft decision output that may be expressed using thefollowing equation:w(e)=log P(ξ|ν)−log P(ξ|ν+e)The event weights, w(e), may be determined using the previously definedequation. As discussed later, the soft decision output may be generatedby using an event weight processor located within the Non-ISIMeta-Viterbi detector 166. The soft decision output may be expressed asfollows: log P(ξ_(i)|ν_(i))−log P(ξ_(i)|{overscore (ν)}_(i)), for i=1, .. . , χ, in which {overscore (ν)}_(i) denotes the complement of the bitν_(i). In the case of additive white Gaussian noise (AWGN), this softdecision output is equal to −(ξ_(i)−ν_(i))²+(ξ_(i)−{overscore(ν)}_(i))². The parity syndrome, π=Φ(ν), of the received codeword may becomputed by the Non-ISI Meta-Viterbi detector 166. The Non-ISIMeta-Viterbi detector 166 utilizes the hard and soft decision outputs todetermine the optimum set of error events for the received codeword. Theerror events are used by the Non-ISI Meta-Viterbi detector 166 todetermine the corrected output, ν⁽⁰⁾ using ν. One may define an errorevent to be a bit sequence of length χ, comprising a single non-zeroelement such that ν+eε{0,1}^(χ), in which the operator “+” denotesconventional arithmetic addition. Various aspects of the presentinvention provide for an error event, comprising a single bit error, tobe specified simply by its bit location within the received codeword.The single bit error event may be expressed in terms of a vector and theset of all possible error events may be specified by the variable G*(ν):G*(ν)={e(D)=±D ^(i) |ν+eε{0,1}^(χ)}The Non-ISI Meta-Viterbi detector 166 determines the probability of anerror event occurring by way of computing one or more event weights,w(e). Since aspects of the invention consider a communication channelwith no ISI, the weight of an error event is based on soft information(i.e, the soft decision output provided by the event weight processor)at the location of the single bit error. However, for the purposes ofexplaining the Meta-Viterbi algorithm, it is sufficient to simply assumethat some strictly positive function w: G*(ν)→(0,∞) exists that maps topositive values. The Non-ISI Meta-Viterbi detector 166 determines theset of error events E={e₁,e₂, . . . ,e_(n)}, E⊂G*(ν), such that itcorrects the parity syndrome, Φ(E):=Φ(e₁)⊕Φ(e₂)⊕ . . . ⊕Φ(e_(n))=π, ofthe received codeword and has minimum weight,${{w(E)}\text{:}} = {\sum\limits_{e \in E}{{w(e)}.}}$

The output of the Non-ISI Meta-Viterbi detector 166 generates an outputthat corresponds to the output of a Viterbi detector using 2^(t) states.The output of the Non-ISI Meta-Viterbi detector 166 may be representedby the following equation which indicates that the hard decision outputis added to one or more error events to provide a corrected output:$v^{(0)} = {v + {\sum\limits_{e \in E}e}}$

FIG. 2 is a functional block diagram describing a computationalcircuitry 208 of a Non-ISI Meta-Viterbi detector (e.g., 166 of FIG. 1B)that is used in determining a preferred set of error events, inaccordance with an embodiment of the invention. The Non-ISI Meta-Viterbidetector comprises the computational circuitry 208. The computationalcircuitry 208 determines the error events eεE and Φ(e)=π≠0, such that:${e = {\arg\quad{\min\limits_{x \in \Omega}\quad{w(x)}}}},{{{where}\quad\Omega} = \{ {{x \in {G^{*}(v)}},{{\Phi(x)} = \pi}} \}}$As illustrated in FIG. 2, the symbol detector (e.g., slicer) 204 outputsa hard decision output, ν, into the computational circuitry 208.Additionally, the noisy codeword, ξ, is input into the symbol detector204 and the computational circuitry 208. The computational circuitry 208determines the preferred error events that have the smallest eventweight for each possible parity syndrome, given t parity bits or 2^(t)states. In FIG. 2, the computational circuitry 208 may also record theparity syndrome values associated with one or more codewords. Theembodiment of FIG. 2 illustrates how the computational circuitry 208determines a preferred set of error events when a four-bit parity codeis used for each codeword. In this representative embodiment, there is apreferred error event associated with each of the 15 possible syndromeswithin a codeword. The preferred error events are considered “locallyminimized”, since their associated event weight is a minimum value forthe associated parity syndrome. Each of the preferred error eventscomprises an error event step in a trellis diagram. Overall, the variousaspects of the present invention may be applied to codewords comprisingone or more parity bits. FIG. 2 provides a representative embodimentillustrating the use of a Meta-Viterbi algorithm using codewords havingan exemplary four bits of parity.

The preferred set of error events for the kth codeword may be denoted bythe following equation: $\begin{matrix}{H = \{ {{e_{\pi}\quad{for}\quad{\forall{\pi \in \{ {0,\quad 1} \}^{t}}}},{\pi \neq {0\text{❘}e_{\quad\pi}}}} } \\{{= {\arg\quad{\min\limits_{\quad{x\quad \in \quad\Omega}}\quad{w(x)}}}},\Omega} \\{ {= \{ {{x \in {G*(v)}},{{\Phi(x)} = \pi}} \}} \}.}\end{matrix}$The events in H may be ordered in sequence based on the parity syndromesthey produce and may be represented by the following equation:H={e₁,e₂,e₃, . . . e₂ _(t) ⁻¹},where Φ(e₁)=(0 . . . 001)ε{0,1}^(t),Φ(e₂)=(0 . . . 010), Φ(e₃)=(0 . . .011), etc.The event weights associated with each preferred error event may beordered according to the parity syndromes produced as follows: {w(e₁),w(e₂), . . . , w(e₂ _(t) ⁻¹)}.The Meta-Viterbi Algorithm, as executed by the Non-ISI Meta-Viterbidetector, charts various subsets of each of the preferred sets of errorevents by way of a Meta-Viterbi trellis diagram. As may be visualizedusing the Meta-Viterbi trellis diagram, every subset of H_(k)corresponds to a path through the Meta-Viterbi trellis.

FIG. 3A is a table illustrating the computation of cumulative parity andcumulative weight of a subset of error events (subset of H={e₁,e₂, . . .,e₁₅}) associated with a four-bit parity codeword, in accordance with anembodiment of the invention. The subset of error events comprises {e₃,e₇, e₁₀, e₁₅}. The exemplary path shown in FIG. 3A corresponds to asequence of error event steps—“no e₁”, “no e₂”, “e₃”, “no e₄”, “no e₅”,etc. The Meta-Viterbi path taken corresponds to a series of error eventdecisions made at each step of the sequence. The second row of the tableprovides the event parity associated with the error event that is taken.The third row of the table provides the event weight associated with theerror event that is taken. The fourth row provides the cumulative parityat each step of the trellis path based on the error events taken. Thefifth row provides the cumulative event weight at each step of the 16state Meta-Viterbi trellis diagram. The Meta-Viterbi trellis comprises2^(t) states and in this embodiment, t=4. Each event parity correspondsto an associated event weight. By way of using the Meta-Viterbi trellis,the path that provides the smallest cumulative event weight for acodeword is chosen given the codeword's parity syndrome. This pathcorresponds to an optimal set of error events that corrects the outputprovided by the symbol detector (e.g., slicer).

FIG. 3B is a diagram illustrating the 16 state Meta-Viterbi trellis pathtaken when the error events chosen correspond to {e₃, e₇, e₁₀, e₁₅}, asdescribed in relation to FIG. 3A, in accordance with an embodiment ofthe invention. Alternatively, the sequence of event choice steps whichforms a path through the trellis may be indicated as follows: “No e₁, Noe₂, e₃, No e₄, No e₅, No e₆, e₇, No e₈, No e₉, e₁₀, No ₁₁, No e₁₂, Noe₁₃, No e₁₄, e₁₅”. The path corresponds to the cumulative parity asdisplayed by the fourth row of the table illustrated in FIG. 3A. Thepath shown is only one representative embodiment of a path taken throughthe 16 state Meta-Viterbi trellis. As illustrated, the path ends With acumulative parity equal to “0001”. The path through the Meta-Viterbitrellis determines the set of error events that may be used to correctthe received codeword generated by the symbol detector. The path takencomprises a path ending with a cumulative parity corresponding to thesyndrome of the codeword.

FIG. 4 illustrates a diagram of a Meta-Viterbi trellis diagram inaccordance with an embodiment of the invention. As shown, step=0 is thestarting point for all paths of a four-bit parity codeword. The variousstates (or cumulative parity) and associated event weights (or pathmetrics) are listed for the three steps illustrated in FIG. 4. Thefollowing three steps list the states, path memory, and path metricassociated with each step of a codeword of a received sequence ofcodewords, for a 16 state Non-ISI Meta-Viterbi detector:

Step 0:

-   -   State (0000): path memory={}, path metric=0    -   Other 15 states (0001) through (1111) are invalid

Step 1:

-   -   State (0000): path memory={}, path metric=0    -   State (0001): path memory={e₁}, path metric=w(e₁)    -   Other 14 states are invalid

Step 2:

-   -   State (0000): path memory={}, path metric =0    -   State (0001): path memory={e}, path metric=w(e₁)    -   State (0010): path memory={e₂}, path metric=w(e₂)    -   State (0011): path memory={e₁,e₂}, path metric=w(e₁)+w(e₂)    -   Other 12 states are invalid        As we progress through the steps, all 16 states become valid and        we start performing ACS operations in a similar fashion as may        be performed using the Viterbi Algorithm. The ACS operations        allow elimination of “non-survivor” paths when determining the        path having the least cumulative event weight.

FIG. 5 is a diagram illustrating the selection of a path having lowestcumulative event weight, when two paths merge in a Meta-Viterbi trellis,in accordance with an embodiment of the invention. As may be seen, thecumulative parity is the same for the two paths (1110). However, theirassociated cumulative weights may differ. For the first path, thecumulative weight is equal to w(e₃)+w(e₇)+w(e₁₀) while in the secondpath, the cumulative weight is equal to w(e₆)+w(e₈). At the merge pointillustrated, each respective path has undergone a sequence of differenterror events. In one instance, the path comprises the error events {e₃,e₇, e₁₀} while in the other instance, the path comprises the errorevents {e₆, e₈}. However, at the end of the path, the two paths meetwith the same cumulative parity. The Non-ISI Meta-Viterbi detectorperforms an add, compare, and select (ACS) operation similar to thatperformed by the Viterbi Algorithm. This process allows elimination of“non-survivor” paths when determining the path with the lowest pathmetric or lowest cumulative event weight. The Non-ISI Meta-Viterbidetector may utilize the following pseudo-language sequence of stepswhich may be used to implement a state machine for performing theMeta-Viterbi Algorithm when constructing a trellis within a codeword:Meta Viterbi algorithm for: State=r(Step=j) The predecessor states areState=r₁ (Step=j−1) State=r₂ (Step=j−1) where r₁ = r⊕Φ(e_(j)),r₂ = r, Ifneither predecessor is valid, the State=r(Step=j) is declared not validIf only one predecessor State=r₁ (Step=j−1) is valid, setPathMemory(State=r, Step=j) = {e_(j)} U PathMemory(State=r₁, Step=j−1)(2) PathMetric(State=r, Step=j) = w(e_(j)) + PathMetric(State=r₁,Step=j−1) (3) If only one predecessor State=r₂ (Step=j−1) is valid, setPathMemory(State=r, Step=j) = PathMemory(State=r₂, Step=j−1) (4)PathMetric(State=r, Step=j) = PathMetric(State=r₂, Step=j−1) (5) If bothpredecessors are valid perform, compare: w(e_(j)) +PathMetric(State=r₁,Step=j−1) vs. PathMetric(State=r₂, Step=j−1) If the left-hand-side issmaller, perform (2) and (3), otherwise perform (4) and (5).As indicated in the pseudo-language above, the Meta-Viterbi algorithmdetermines the sequence of error events by using the PathMemoryvariable. The Meta-Viterbi algorithm determines the path metric orcumulative event weight by using the PathMetric variable. When the pathsmerge, the Meta-Viterbi algorithm performs a comparison between the twopath metrics associated with the two paths. It determines the pathmetric that has the smaller value and subsequently stores the associatedsequence of error events and path metric. Since we need to enforce theparity of the codeword, at Step=2^(t)−1 only State=π is valid.

FIG. 6 is a functional block diagram of a Non-ISI Meta-Viterbi detector604 in accordance with an embodiment of the invention. The Non-ISIMeta-Viterbi detector 604 comprises an event weight processor 608, acomputational circuitry 612, a parity syndrome calculator 616, and anerror correction circuitry 620. The event weight processor 608 iscapable of computing one or more event weights, w(e), of a trellis. Asmentioned earlier, the event weight may be computed using the followingequation:w(e)=log P(ξ|ν)−log P(ξ|ν+e).Further, the soft decision output may be expressed as follows:log P(ξ_(i)|ν_(i))−log P(ξ_(i)|{overscore (ν)}_(i)), for i=1, . . . ,χ,in which {overscore (ν)}_(i) denotes the complement of the bit ν_(i).This equation may be further simplified when the noise introduced by thechannel is AWGN. In the case of additive white Gaussian noise (AWGN),this soft decision output is equal to −(ξ_(i)−ν_(i))²+(ξ_(i)−{overscore(ν)}_(i))². The computational circuitry 612 is capable of computing oneor more parameters associated with a Meta-Viterbi trellis. The symboldetector (e.g., slicer) provides hard decision information which is usedby the event weight processor 608. The symbol detector also provides thehard decision information used by the parity syndrome calculator 616.The event weight processor 608 uses as inputs, the hard decision outputprovided by the symbol detector and the one or more noisy receivedcodewords, ξ. The computational circuitry 612 determines the errorevents that have the smallest event weights for each parity syndrome ofa particular received codeword. The parity syndrome calculator 616computes the parity syndrome values associated with the one or morereceived codewords. The parity syndrome calculator 616 processes theoutput provided by the symbol detector and outputs the parity syndromevalues to the computational circuitry 612. As illustrated, thecomputational circuitry 612 receives event weights computed by the eventweight processor 608 and the values calculated by the parity syndromecalculator 616. The computational circuitry 612 may determine one ormore optimal paths taken using a trellis diagram. One of the one or moreoptimal paths corresponds to a path having minimum cumulative eventweight. The computational circuitry 612 may compute the cumulativeparity of the sequence of error events. The computational circuitry 612may perform one or more ACS operations when determining one or morecumulative event weights of one or more paths in the trellis diagram.The computational circuitry 612 may compute one or more event weightsassociated with one or more error events of a codeword. Additionally,the computational circuitry 612 may compute one or more cumulative eventweights associated with one or more codewords. The error correctioncircuitry 620 corrects the one or more received codewords by determiningthe appropriate set of error events to add to the one or more receivedcodewords. The error correction circuitry 620 may utilize the set oferror events associated with the optimal path having a minimumcumulative event weight. The event weight processor 608, computationalcircuitry 612, parity syndrome calculator 616, and error correctioncircuitry 620 may comprise any type of digital logic circuitry used toimplement an appropriate state-machine.

While the invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the invention without departing from its scope.Therefore, it is intended that the invention not be limited to theparticular embodiments disclosed, but that the invention will includeall embodiments falling within the scope of the appended claims.

1. A method of detecting and correcting data bit errors in one or morereceived codewords transmitted through a communication channelcomprising: first processing said one or more received codewords using asymbol detector; generating one or more outputs from said symboldetector; and second processing said output using a Non-ISI Meta-Viterbidetector having 2^(t) states, said communication channel providing nointersymbol interference.
 2. The method of claim 1 wherein said usingsaid symbol detector and said using said Non-ISI Meta-Viterbi detectorhaving 2^(t) states provides performance equivalent to that of a Viterbidetector having 2^(t) states.
 3. The method of claim 2 wherein saidNon-ISI Meta-Viterbi detector uses χ+2^(t)2^(t) add, compare, and selectoperations.
 4. The method of claim 1 wherein said one or more outputscomprises a hard decision output, ν, wherein$v = {{\underset{x \in {\{{0,1}\}}^{\chi}}{\arg\quad\max}\quad\log\quad{P( {\xi\text{❘}x} )}}\quad = {\underset{x \in {\{{0,1}\}}^{\chi}}{argmax}{\sum\limits_{i = 1}^{i = \chi}{\log\quad{{P( {\xi_{i}\text{❘}x_{i}} )}.}}}}}$5. The method of claim 4 wherein said Non-ISI Meta-Viterbi detectorprovides a soft decision output, log P(ξ_(i)|ν_(i))−logP(ξ_(i)|{overscore (ν)}_(i)), for i=1, . . . ,χ.
 6. The method of claim5 wherein log P(ι_(i)|ν_(i))−log P(ξ_(i)|{overscore (ν)}_(i)), for i=1,. . . ,χ equates to −(ξ_(i)−ν_(i))²+(ξ_(i)−{overscore (ν)}_(i))² in thenoise added to said communication channel is additive white Gaussian. 7.The method of claim 6 wherein said Non-ISI Meta-Viterbi detector usessaid hard and said soft decision outputs to correct said one or morereceived codewords.
 8. The method of claim 7 wherein a linear operator,Φ:{0,1}^(χ)→{0,1}^(t), computes the parity syndrome value of said harddecision output such that Φ(E):=Φ(e₁)⊕Φ(e₂)⊕ . . . ⊕Φ(e_(n))=π, whereinthe sum of the event weights represented by said set of error events hasa minimum value.
 9. The method of claim 8 wherein one or more preferrederror events are determined for each said received codeword such thatthe following conditions apply:${e \in E},{{{and}\quad{\Phi(e)}} = {\pi \neq 0}},{{{and}\quad e} = {\arg\quad{\min\limits_{\quad{x \in \Omega}}\quad{w(x)}}}},{{{where}\quad\Omega} = {\{ {{x \in {G^{*}(v)}},{{\Phi(x)} = \pi}} \}.}}$10. The method of claim 1 wherein said second processing comprises:constructing a trellis diagram for each said received codeword of saidone or more codewords using branches determined from one or more sets ofevent choice steps; determining a path of said trellis diagramassociated with a minimum cumulative event weight; and correcting saideach said received codeword.
 11. The method of claim 10 wherein saidminimum cumulative event weight of said trellis diagram for each of saidreceived codeword is equal to its parity syndrome.
 12. The method ofclaim 1 wherein each of said one or more codewords comprises t paritybits.
 13. The method of claim 1 wherein said communication channelcomprises a wireline data communication channel.
 14. A method ofcorrecting one or more data bit errors in a received codeword of acommunications channel, said method comprising: determining one or moreerror events,${e = {\arg\quad{\min\limits_{x \in \Omega}\quad{w(x)}}}},{{{where}\quad\Omega} = \{ {{x \in {G^{*}(v)}},{{\Phi(x)} = \pi}} \}}$of said received codeword wherein$v = {{\underset{x \in {\{{0,1}\}}^{\chi}}{\arg\quad\max}\quad\log\quad{P( \xi \middle| x )}} = {\underset{x \in {\{{0,1}\}}^{\chi}}{\arg\quad\max}{\sum\limits_{i = 1}^{i = \chi}{\log\quad{P( \xi_{i} \middle| x_{i} )}}}}}$and ξ represents a sequence of noisy received codewords, said one ormore error events used to correct said one or more data bit errors usinga linear operator that computes one or more parity syndromes of said oneor more error events, said linear operator operating on said one or moreerror events, such that Φ(E):=Φ(e₁)⊕Φ(e₂)⊕ . . . ⊕χ(e_(n))=π.determining one or more preferred error events associated with said oneor more parity syndromes; using said one or more preferred error eventsto construct a trellis diagram; and selecting a path of said trellisdiagram associated with a minimum cumulative event weight, saidcommunications channel not capable of providing any intersymbolinterference.
 15. The method of claim 14 wherein said minimum cumulativeevent is equal to the sum of the event weights associated with said pathof said trellis diagram, said minimum cumulative event weight defined bythe following equation: ${w(E)}:={\sum\limits_{e \in E}{{w(e)}.}}$ 16.The method of claim 14 wherein each of said one or more preferred errorevents corresponds to a parity syndrome whose event weight has minimumvalue.
 17. The method of claim 14 wherein said minimum cumulative eventweight is used to correct said received codeword.
 18. The method ofclaim 14 wherein said communications channel incorporates noise that isindependent, identically distributed, additive white Gaussian.
 19. Asystem for detecting and correcting data bit errors in one or morereceived codewords transmitted through a communication channelcomprising: a symbol detector that processes said one or more receivedcodewords; and a Non-ISI Meta-Viterbi detector that processes said oneor more received codewords processed by said symbol detector, saidNon-ISI Meta-Viterbi detector used for computing event parity syndromes,associated event weights, and cumulative event weights, and forperforming add, compare, and select operations, said communicationchannel not generating any intersymbol interference.
 20. The system ofclaim 19 wherein said Non-ISI Meta-Viterbi detector comprises: an eventweight processor; a computational circuitry; a parity syndromecalculator; and an error correction circuitry used to correct one ormore said data bit errors in said one or more received codewords. 21.The system of claim 20 wherein said event weight processor,computational circuitry, parity syndrome calculator, and errorcorrection circuitry are implemented using digital logic circuitry. 22.The system of claim 19 wherein said symbol detector comprises a slicer.23. The system of claim 19 wherein said Non-ISI Meta-Viterbi detectorperforms χ+2^(t)2^(t) add, compare, and select operations.